1. Field of the Invention
This invention relates to DLLs, and more particularly, to DLLs in memories that have a wide frequency application.
2. Description of the Prior Art
Many memory devices incorporate Delay Locked Loops (DLLs) which contain an internal delay loop/delay line that locks to an external clock rate. The DLLs are used to eliminate clock insertion delay. A typical example of a memory type that uses a DLL is Double Data Rate (DDR) memories, which are next generation memory devices that transfer data on both rising and falling edges of a clock signal.
Please refer to FIG. 1. FIG. 1 is a diagram of a conventional DLL system 100 in a memory. As shown in the diagram, the DLL system 100 includes a DLL delay line 150 that has a fixed power supply supplied by a bias generator 120 coupled to a power regulator 130. The DLL delay line 150 is further coupled to an RCV buffer 110 that is the clock receiver for the DLL system 100, and receives a differential clock signal VCLK and \VCLK. The amount of delay will be according to the operating frequency of the DLL system 100; at higher operating frequencies, only a few delay elements in the delay line will be used, so there is less delay between the external and internal clock. At lower frequencies, the entire delay line 150 will be used. The operating frequency range of a memory that uses a DLL is therefore limited by the number of delay elements within the DLL.
Most memory systems have an operating range according to the JEDEC spec, which is a specification used in the field that provides standardized operating parameters for memories. For example, a DDR3 memory device has a recommended clock frequency range of 800 MHz 1600 MHz. Although it is possible for memories to operate outside this frequency range (when power saving is required, for example), this would necessitate increasing the typical number of delay elements within the delay line 150. The subsequent increase in space required for the DLL delay line 150 means this solution is usually not implemented by manufacturers. A second option is to bypass the DLL system 100 entirely when operating at lower frequencies. In conventional memories, the DLL system 100 would need to be disabled. In doing so, data output timing will no longer be the same as when the DLL system 100 is enabled and there is a risk that the accuracy of the memory will be adversely affected to an undesirable degree.
With this in mind, there is a need for a DLL system to be used in a memory that can operate outside the standard operating frequency range of the memory without increasing the number of delay elements within the DLL system or disabling the DLL system during low (or high) frequency operation.